1. Field of the Invention
The invention relates to a semiconductor integrated circuit, and more particularly to a CMOS semiconductor integrated circuit of a gate array type or a standard cell type.
2. Description of the Related Art
A transistor having a lightly doped drain (LDD) structure is quite often used in recent CMOS logic LSI in order to prevent that the transistor's performance is deteriorated due to the presence of hot carriers. A LDD transistor is provided with an area having a lower concentration of impurities than a source/drain area between the source/drain area and a channel area located beneath a gate or side walls, to thereby suppress the generation of hot carriers.
In an application specific IC (ASIC) such as a sea-of-gates (SOG) gate array and a standard cell type LSI, all of LDD transistors included in an internal basic cell are provide with an LDD area at both source and drain sides. Namely, a source and a drain have a symmetrical structure with respect to a gate.
Such a symmetrical structure makes it possible to use a diffusion layer, in which a MOS transistor is formed, as a source or a drain in LSI, more particularly in random logic of an SOG gate array or a standard cell, in which a transistor array is in advance formed on a silicon wafer, and then a logic is constituted by patterning lead wires. This reduces the number of transistors to be used in a basic cell, and thereby reduces a size of a basic cell.
On the other hand, once a circuit structure has been defined by patterning of lead wires in a conventional basic cell as above mentioned, the basic cell would have an LDD area at a source side, which LDD area does not contribute to the enhancement of the resistance of a basic cell against hot carrier resistance. This LDD area reduces an amount of on-current and further retards an operation speed of a basic cell due to a presence of a resistance located in the LDD area at a source side.
FIG. 1 schematically illustrates resistors of a P-channel MOS transistor having LDD structures located symmetrically about a gate.
In an LDD transistor, an LDD area is formed by ion implantation after a gate has been patterned, and source and drain areas are formed by ion implantation of a source and a drain after sidewalls have been formed. Between a source 804 and a drain 805 both of which are in "on" condition, five resistors are connected in series with each other; namely, a source contact resistor and source diffusion layer resistor 812, a resistor 813 of an LDD area at the side of a source, a channel resistor 814, a resistor 815 of an LDD area at the side of a drain, and a drain contact resistor and drain diffusion layer resistor 816.
Presently, in a transistor having a gate which is 0.5 .mu.m long, when a transistor is in "on" condition, the resistors 813 and 815 located in the LDD area reach about 10% at one side relative to total resistances located between a source and a drain. Accordingly, if the resistors located in the LDD area at the side of a source are eliminated and a source diffusion layer is extended to beneath a sidewall located at a source side, it would be possible to increase on-current corresponding to the above mentioned "10%" of the resistors.
With reference to FIG. 2 illustrating a layout of a basic cell array of a conventional CMOS transistor SOG, a conventional basic cell 603 comprises two P-channel MOS transistors 608a and 608b and two N-channel MOS transistors 609a and 609b. With reference to FIG. 3 which is a cross-sectional view of the P-channel MOS transistor taken along the line A--A in FIG. 2, the illustrated conventional semiconductor integrated circuit has a P-type substrate 610 and an N-well 611 formed on the P-substrate 610. To the N-well 611 is supplied a source voltage from an N-well contact diffusion layer 604. The two P-channel MOS transistors 608a and 608b share a P+ diffusion layer 606b to thereby be connected in series with each other. Each of P-channel MOS transistors 608a and 608b has sidewalls 613 at opposite sides of a gate. Beneath the sidewalls 613 are formed P-LDD areas 614. Each of the N-channel MOS transistors 609a and 609b in the basic cell 603 has the same structure as the P-channel MOS transistor 608a or 608b.
FIG. 4 illustrates an embodiment of double inputs NAND formed on the basic cell array illustrated in FIG. 2, and FIG. 5 illustrates an equivalent circuit to a circuit of FIG. 4. In FIG. 5, two P-channel MOS transistors 708a and 708b are connected in parallel with each other between a power source 710 and an output terminal 714. Namely, there is added at a side of a source to the circuit of FIG. 5 an LDD resistor which does not contribute to the enhancement of the resistance against hot carriers. This source-side LDD resistor reduces the drivability of the circuit and also retards the operation speed of the circuit.
As having explained so far, a conventional cell has a structure in which the impurities concentration is distributed symmetrically about a gate between a source and a drain of a transistor. Consequently, there must be formed at a side of a source an LDD area which does not contribute to the enhancement of the resistance of a transistor against hot carriers. The resistors in the source-side LDD area are connected in series with a source and a drain when a transistor is being operated, and thereby an on-current of a transistor is reduced correspondingly to the source-side LDD resistors, and the operation speed of a transistor is retarded.